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| a FEATURES Single-Supply Operation: 2.7 Volts to 6 Volts High Output Current: 250 mA Low Supply Current: 750 A/Amplifier Wide Bandwidth: 3 MHz Slew Rate: 5 V/ s No Phase Reversal Low Input Currents Unity Gain Stable Rail-to-Rail Input and Output APPLICATIONS Multimedia Audio LCD Driver ASIC Input or Output Amplifier Headphone Driver GENERAL DESCRIPTION Low Cost, 250 mA Output Single-Supply Amplifiers AD8531/AD8532/AD8534 PIN CONFIGURATIONS 5-Lead SC70 and SOT-23 (KS and RT Suffixes) OUT A 1 V AD8531 5 V+ 2 4 IN A +IN A 3 8-Lead SOIC, TSSOP, and MSOP (R, RU, and RM Suffixes) NULL 1 -IN A +IN A V- 2 3 4 AD8531 8 7 6 5 NC V+ OUT A NULL The AD8531, AD8532, and AD8534 are single, dual and quad rail-to-rail input and output single-supply amplifiers featuring 250 mA output drive current. This high output current makes these amplifiers excellent for driving either resistive or capacitive loads. AC performance is very good with 3 MHz bandwidth, 5 V/ms slew rate and low distortion. All are guaranteed to operate from a 3 volt single supply as well as a 5 volt supply. The very low input bias currents enable the AD853x to be used for integrators, diode amplification and other applications requiring low input bias current. Supply current is only 750 mA per amplifier at 5 volts, allowing low current applications to control high current loads. Applications include audio amplification for computers, sound ports, sound cards and set-top boxes. The AD853x family is very stable and capable of driving heavy capacitive loads, such as those found in LCDs. The ability to swing rail-to-rail at the inputs and outputs enables designers to buffer CMOS DACs, ASICs or other wide output swing devices in single-supply systems. The AD8531, AD8532, and AD8534 are specified over the extended industrial (-40C to +85C) temperature range. The AD8531. The AD8532 is available in 8-lead SOIC, MSOP, TSSOP surface-mount packages. The AD8534 is available in narrow SO-14 and 14-lead TSSOP surface-mount packages. All TSSOP, SOT, and SC70 versions are available in tape and reel only. 8-Lead SOIC, TSSOP, and MSOP (R, RU, and RM Suffixes) OUT A -IN A +IN A V- 1 2 3 4 AD8532 8 7 6 5 V+ OUT B -IN B +IN B 14-Lead SOIC, and TSSOP (R, and RU Suffixes) OUT A -IN A +IN A V+ +IN B -IN B OUT B 1 2 3 4 5 6 7 14 OUT D 13 -IN D 12 +IN D AD8534 11 V- 10 +IN C 9 8 -IN C OUT C REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002 AD8531/AD8532/AD8534-SPECIFICATIONS ELECTRICAL CHARACTERISTICS (@ V = 3.0 V, V S CM = 1.5 V, TA = 25 C unless otherwise noted) Min Typ Max 25 30 50 60 25 30 3 Unit mV mV pA pA pA pA V dB V/mV mV/C fA/C fA/C V V mV mV mA W dB mA mA V/ms ms MHz Degrees dB nV//Hz nV//Hz pA//Hz Parameter INPUT CHARACTERISTICS Offset Voltage Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain Offset Voltage Drift Bias Current Drift Offset Current Drift OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low Output Current Closed-Loop Output Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Settling Time Gain Bandwidth Product Phase Margin Channel Separation NOISE PERFORMANCE Voltage Noise Density Current Noise Density Specifications subject to change without notice. Symbol VOS IB IOS CMRR AVO DVOS/DT DIB/DT DIOS/DT VOH VOL IOUT ZOUT PSRR ISY Conditions -40C TA +85C -40C TA +85C -40C TA +85C VCM = 0 V to 3 V RL = 2 kW, VO = 0.5 V to 2.5 V 0 38 5 1 45 25 20 50 20 2.92 60 250 60 100 125 IL = 10 mA -40C TA +85C IL = 10 mA -40C TA +85C f = 1 MHz, AV = 1 VS = 3 V to 6 V VO = 0 V -40C TA +85C RL = 2 kW To 0.01% 2.85 2.8 45 55 0.70 1 1.25 SR tS GBP fo CS en in f = 1 kHz, RL = 2 kW f = 1 kHz f = 10 kHz f = 1 kHz 3.5 1.6 2.2 70 65 45 30 0.05 -2- REV. D AD8531/AD8532/AD8534 ELECTRICAL CHARACTERISTICS (@ V = 5.0 V, V S CM = 2.5 V, TA = 25 C unless otherwise noted) Min Typ Max 25 30 50 60 25 30 5 Unit mV mV pA pA pA pA V dB V/mV mV/C fA/C fA/C V V mV mV mA W dB mA mA V/ms kHz ms MHz Degrees dB nV//Hz nV//Hz pA//Hz Parameter INPUT CHARACTERISTICS Offset Voltage Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain Offset Voltage Drift Bias Current Drift Offset Current Drift OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low Output Current Closed-Loop Output Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Full-Power Bandwidth Settling Time Gain Bandwidth Product Phase Margin Channel Separation NOISE PERFORMANCE Voltage Noise Density Current Noise Density Specifications subject to change without notice. Symbol VOS IB IOS CMRR AVO DVOS/DT DIB/DT DIOS/DT VOH VOL IOUT ZOUT PSRR ISY Conditions -40C TA +85C -40C TA +85C -40C TA +85C VCM = 0 V to 5 V RL = 2 kW, VO = 0.5 V to 4.5 V -40C TA +85C 0 38 15 5 1 47 80 20 50 20 4.94 50 250 40 100 125 IL = 10 mA -40C TA +85C IL = 10 mA -40C TA +85C f = 1 MHz, AV = 1 VS = 3 V to 6 V VO = 0 V -40C TA +85C RL = 2 kW 1% Distortion To 0.01% 4.9 4.85 45 55 0.75 1.25 1.75 SR BWp tS GBP fo CS en in f = 1 kHz, RL = 2 kW f = 1 kHz f = 10 kHz f = 1 kHz 5 350 1.4 3 70 65 45 30 0.05 REV. D -3- AD8531/AD8532/AD8534 ABSOLUTE MAXIMUM RATINGS 1 PACKAGE INFORMATION Supply Voltage (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND to VS Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . 6 V Storage Temperature Range . . . . . . . . . . . . -65C to +150C Operating Temperature Range . . . . . . . . . . . -40C to +85C Junction Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 For supplies less than +6 volts, the differential input voltage is equal to VS. Package Type 5-Lead SC70 (KS) 5-Lead SOT-23 (RT) 8-Lead SOIC (RN) 8-Lead MSOP (RM) 8-Lead TSSOP (RU) 14-Lead SOIC (RN) 14-Lead TSSOP (RU) JA* JC Unit C/W C/W C/W C/W C/W C/W C/W 376 230 158 210 240 120 240 126 146 43 45 43 36 43 *qJA is specified for the worst case conditions, i.e., qJA is specified for device in socket for P-DIP packages; qJA is specified for device soldered onto a circuit board for surface-mount packages. ORDERING GUIDE Model AD8531AKS* AD8531AR AD8531ART* AD8532AR AD8532ARM* AD8532ARU* AD8534AR AD8534ARU* *Available in reels only. Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 5-Lead SC70 8-Lead SOIC 5-Lead SOT-23 8-Lead SOIC 8-Lead MSOP 8-Lead TSSOP 14-Lead SOIC 14-Lead TSSOP Package Option KS-5 RN-8 RT-5 RN-8 RM-8 RU-8 RN-14 RU-14 Branding Information A7B A7A ARA CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8531/AD8532/AD8534 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE 2.5 -VOL 2 +VOH VOUT 1.5 1 0.5 0 0 20 40 60 80 100 120 RLOAD - 140 160 180 200 Figure 1. Output Voltage vs. Load. VS = 2.5 V, RL Is Connected to GND (0 V) -4- REV. D Typical Performance Characteristics-AD8531/AD8532/AD8534 VS = 2.7V 500 QUANTITY - Amplifiers VS = 5V 500 QUANTITY - Amplifiers TA = 25 C TA = 25 C 400 INPUT OFFSET VOLTAGE - mV VCM = 1.35V VCM = 2.5V -2 -3 -4 -5 -6 -7 -8 VS = 5V VCM = 2.5V 400 300 300 200 200 100 100 -12 -10 -8 -6 -4 -2 0 2 4 INPUT OFFSET VOLTAGE - mV -12 -10 -8 -6 -4 -2 0 2 4 INPUT OFFSET VOLTAGE - mV -35 -15 5 25 45 65 TEMPERATURE - C 85 Figure 2. Input Offset Voltage Distribution Figure 3. Input Offset Voltage Distribution Figure 4. Input Offset Voltage vs. Temperature 6 8 VS = 5V, 3V VS = 5V 7 6 5 4 3 2 INPUT BIAS CURRENT - pA 8 7 6 5 4 3 2 1 INPUT OFFSET CURRENT - pA INPUT BIAS CURRENT - pA VCM = VS/2 TA = 25 C 5 4 3 2 1 0 -1 VS = 5V, 3V VCM = VS/2 -35 -15 5 25 45 65 TEMPERATURE - C 85 -2 0 1 2 3 4 5 COMMON-MODE VOLTAGE - Volts -35 -15 5 25 45 65 TEMPERATURE - C 85 Figure 5. Input Bias Current vs. Temperature Figure 6. Input Bias Current vs. Common-Mode Voltage Figure 7. Input Offset Current vs. Temperature 1000 10000 VS = 2.7V TA = 25 C OUTPUT VOLTAGE - mV 1000 VS = 5V TA = 25 C 80 SOURCE 10 SINK VS = 2.7V RL = NO LOAD TA = 25 C 60 40 20 0 45 90 135 180 OUTPUT VOLTAGE - mV 10 SINK 1 1 0.1 0.01 0.1 1 10 100 LOAD CURRENT - mA 1000 0.01 0.01 0.1 1 10 100 LOAD CURRENT - mA 1000 GAIN - dB SOURCE 100 1k 10k 100k 1M 10M FREQUENCY - Hz 100M Figure 8. Output Voltage to Supply Rail vs. Load Current Figure 9. Output Voltage to Supply Rail vs. Load Current Figure 10. Open-Loop Gain and Phase vs. Frequency REV. D -5- PHASE SHIFT - Degrees 100 AD8531/AD8532/AD8534 VS = 5V RL = NO LOAD 5 VS = 2.7V TA = 25 C OUTPUT SWING - Volts p-p RL = 2k VIN = 2.5V p-p 5 VS = 5V 4 TA = 25 C RL = 2k VIN = 4.9V p-p 3 80 GAIN - dB 60 40 20 0 PHASE SHIFT - Degrees OUTPUT SWING - Volts p-p TA = 25 C 4 45 90 135 180 3 2 2 1 1 0 1k 10k 100k 1M 10M FREQUENCY - Hz 100M 1k 10k 100k 1M FREQUENCY - Hz 10M 0 1k 10k 100k 1M FREQUENCY - Hz 10M Figure 11. Open-Loop Gain & Phase vs. Frequency Figure 12. Closed-Loop Output Voltage Swing vs. Frequency Figure 13. Closed-Loop Output Voltage Swing vs. Frequency 200 180 160 140 VS = 5V TA = 25 C 100 V/div 100 90 VS = 5V AV = 1000 TA = 25 C FREQUENCY = 1kHz 100 90 VS = 5V A V = 1000 TA = 25 C FREQUENCY = 10kHz IMPEDANCE - 120 100 80 60 40 20 0 1k AV = 10 AV = 1 200 V/div 10 0% 10 0% MARKER 41 V/ Hz 10k 100k 1M 10M FREQUENCY - Hz 100M MARKER 25.9 V/ Hz Figure 14. Closed-Loop Output Impedance vs. Frequency Figure 15. Voltage Noise Density vs. Frequency Figure 16. Voltage Noise Density vs. Frequency 1 110 140 POWER SUPPLY REJECTION - dB VS = 5V TA = 25 C CURRENT NOISE DENSITY - pA/ Hz COMMON-MODE REJECTION - dB VS = 5V TA = 25 C 100 90 80 70 60 50 40 1k 120 100 80 60 40 20 0 -20 -40 -60 100 VS = 2.7V TA = 25 C 0.1 PSRR- PSRR+ 0.01 10 100 1k 10k FREQUENCY - Hz 100k 10k 100k 1M FREQUENCY - Hz 10M 1k 10k 100k 1M FREQUENCY - Hz 10M Figure 17. Current Noise Density vs. Frequency Figure 18. Common-Mode Rejection vs. Frequency Figure 19. Power Supply Rejection vs. Frequency -6- REV. D AD8531/AD8532/AD8534 140 POWER SUPPLY REJECTION - dB SMALL SIGNAL OVERSHOOT - % 100 80 60 40 20 0 -20 -40 -60 100 1k 100k 10k FREQUENCY - Hz 1M 10M PSRR+ PSRR- 40 TA = 25 C RL = 2k SMALL SIGNAL OVERSHOOT - % 120 VS = 5V TA = 25 C 50 VS = 2.7V 60 50 40 -OS 30 +OS 20 VS = 5V TA = 25 C RL = 2k 30 -OS 20 +OS 10 10 0 10 100 1000 CAPACITANCE - pF 10000 0 10 100 1000 CAPACITANCE - pF 10000 Figure 20. Power Supply Rejection vs. Frequency Figure 21. Small Signal Overshoot vs. Load Capacitance Figure 22. Small Signal Overshoot vs. Load Capacitance 50 50 0.9 SUPPLY CURRENT/AMPLIFIER - mA SMALL SIGNAL OVERSHOOT - % 40 SMALL SIGNAL OVERSHOOT - % VS = 5V TA = 25 C RL = 600 40 VS = 2.7V TA = 25 C RL = 600 0.85 0.8 0.75 0.7 0.65 0.6 VS = 3V 0.55 0.5 -40 VS = 5V 30 -OS +OS 30 20 20 -OS 10 +OS 0 10 100 1000 CAPACITANCE - pF 10000 10 0 10 100 1000 CAPACITANCE - pF 10000 -20 0 20 40 60 TEMPERATURE - C 80 Figure 23. Small Signal Overshoot vs. Load Capacitance Figure 24. Small Signal Overshoot vs. Load Capacitance Figure 25. Supply Current per Amplifier vs. Temperature 0.80 SUPPLY CURRENT/AMPLIFIER - mA 0.70 0.60 TA = 25 C 20mV/DIV 0.40 0.30 0.20 0.10 0.00 0.75 1.00 1.50 2.00 SUPPLY VOLTAGE - 2.50 Volts 3.00 0V 20mV/DIV 0.50 VS = 1.35V VIN = 50mV AV = 1 RL = 2k CL = 300pF TA = 25 C 0V VS = 2.5V VIN = 50mV AV = 1 RL = 2k CL = 300pF TA = 25 C 500 ns/DIV 500 ns/DIV Figure 26. Supply Current per Amplifier vs. Supply Voltage Figure 27. Small Signal Transient Response Figure 28. Small Signal Transient Response REV. D -7- AD8531/AD8532/AD8534 100 90 VS = 2.5V AV = 1 RL = 2k TA = 25 C 100 90 VS = 1.35V AV = 1 RL = 2k TA = 25 C 1V 100 90 10 s 10 0% 10 0% 10 0% 500mV 500ns 500mV 500ns 1V Figure 29. Large Signal Transient Response Figure 30. Large Signal Transient Response Figure 31. No Phase Reversal V+ APPLICATIONS THEORY OF OPERATION The AD8531/AD8532/AD8534 is an all-CMOS, high output current drive, rail-to-rail input/output operational amplifier. This is the latest entry in Analog Devices' expanding family of single-supply devices for the multimedia and telecom marketplaces. Its high output current drive and stability with heavy capacitive loads makes the AD8531/AD8532/AD8534 an excellent choice as a drive amplifier for LCD panels. Figure 32 illustrates a simplified equivalent circuit for the AD8531/ AD8532/AD8534. Like many rail-to-rail input amplifier configurations, it is comprised of two differential pairs, one n-channel (M1-M2) and one p-channel (M3-M4). These differential pairs are biased by 50 mA current sources, each with a compliance limit of approximately 0.5 V from either supply voltage rail. The differential input voltage is then converted into a pair of differential output currents. These differential output currents are then combined in a compound folded-cascade second gain stage (M5-M9). The outputs of the second gain stage at M8 and M9 provide the gate voltage drive to the rail-to-rail output stage. Additional signal current recombination for the output stage is achieved through the use of transistors M11-M14. In order to achieve rail-to-rail output swings, the AD8531/ AD8532/AD8534 design employs a complementary commonsource output stage (M15-M16). However, the output voltage swing is directly dependent on the load current, as the difference between the output voltage and the supply is determined by the AD8531/AD8532/AD8534's output transistors on-channel resistance (see Figures 8 and 9). The output stage also exhibits voltage gain by virtue of the use of common-source amplifiers; as a result, the voltage gain of the output stage (thus, the openloop gain of the device) exhibits a strong dependence to the total load resistance at the output of the AD8531/AD8532/AD8534. 50 A 100 A 100 A M11 20 A M5 VB2 M1 IN- M3 M4 M2 M8 M12 M15 OUT IN+ M6 VB3 M9 20 A 50 A M7 M10 M13 M14 M16 V- Figure 32. AD8531/AD8532/AD8534 Simplified Equivalent Circuit Short-Circuit Protection As a result of the design of the output stage for maximum load current capability, the AD8531/AD8532/AD8534 does not have any internal short-circuit protection circuitry. Direct connection of the AD8531/AD8532/AD8534's output to the positive supply in single-supply applications will destroy the device. In those applications where some protection is needed, but not at the expense of reduced output voltage headroom, a low value resistor in series with the output, as shown in Figure 33, can be used. The resistor, connected within the feedback loop of the amplifier, will have very little effect on the performance of the amplifier other than limiting the maximum available output voltage swing. For single 5 V supply applications, resistors less than 20 W are not recommended. 5V VIN RX 20 AD8532 VOUT Figure 33. Output Short-Circuit Protection -8- REV. D AD8531/AD8532/AD8534 Power Dissipation Power Calculations for Varying or Unknown Loads Although the AD8531/AD8532/AD8534 is capable of providing load currents to 250 mA, the usable output load current drive capability will be limited to the maximum power dissipation allowed by the device package used. In any application, the absolute maximum junction temperature for the AD8531/ AD8532/AD8534 is 150C, and should never be exceeded for the device could suffer premature failure. Accurately measuring power dissipation of an integrated circuit is not always a straightforward exercise, so Figure 34 has been provided as a design aid for either setting a safe output current drive level or in selecting a heatsink for the package options available on the AD8531/AD8532/AD8534. 1.5 TJ MAX = 150 C FREE AIR NO HEATSINK Often, calculating power dissipated by an integrated circuit to determine if the device is being operated in a safe range is not as simple as it might seem. In many cases power cannot be directly measured. This may be the result of irregular output waveforms or varying loads; indirect methods of measuring power are required. There are two methods to calculate power dissipated by an integrated circuit. The first can be done by measuring the package temperature and the board temperature. The other is to directly measure the circuit's supply current. Calculating Power by Measuring Ambient and Case Temperature Given the two equations for calculating junction temperature: TJ = TA + P qJA where TJ is junction temperature, and TA is ambient temperature. qJA is the junction to ambient thermal resistance. TJ = TC + P qJC where TC is case temperature and qJA and qJC are given in the data sheet. The two equations can be solved for P (power): TA + P qJA = TC + P qJC P = (TA - TC )/ (qJC - qJA) Once power has been determined it is necessary to go back and calculate the junction temperature to assure that it has not been exceeded. The temperature measurements should be directly on the package and on a spot on the board that is near the package but definitely not touching it. Measuring the package could be difficult. A very small bimetallic junction glued to the package could be used or it could be done using an infrared sensing device if the spot size is small enough. Calculating Power by Measuring Supply Current POWER DISSIPATION - Watts 1 SOIC JA = 158 C/W TSSOP JA = 240 C/W 0.5 SOT-23 JA = 236 C/W SC70 JA = 376 C/W 0 0 25 50 TEMPERATURE - C 75 85 100 Figure 34. Maximum Power Dissipation vs. Ambient Temperature These thermal resistance curves were determined using the AD8531/AD8532/AD8534 thermal resistance data for each package and a maximum junction temperature of 150C. The following formula can be used to calculate the internal junction temperature of the AD8531/AD8532/AD8534 for any application: TJ = PDISS qJA + TA where TJ = junction temperature; PDISS = power dissipation; qJA = package thermal resistance, junction-to-case; and TA = Ambient temperature of the circuit. To calculate the power dissipated by the AD8531/AD8532/ AD8534, the following equation can be used: PDISS = ILOAD (VS-VOUT) where ILOAD = is output load current; VS = is supply voltage; and VOUT = is output voltage. The quantity within the parentheses is the maximum voltage developed across either output transistor. As an additional design aid in calculating available load current from the AD8531/AD8532/AD8534, Figure 1 illustrates the AD8531/ AD8532/AD8534 output voltage as a function of load resistance. Power can be calculated directly knowing the supply voltage and current. However, supply current may have a dc component with a pulse into a capacitive load. This could make rms current very difficult to calculate. It can be overcome by lifting the supply pin and inserting an rms current meter into the circuit. For this to work you must be sure all of the current is being delivered by the supply pin you are measuring. This is usually a good method in a single supply system; however, if the system uses dual supplies, both supplies may need to be monitored. Input Overvoltage Protection As with any semiconductor device, whenever the condition exists for the input to exceed either supply voltage, the device's input overvoltage characteristic must be considered. When an overvoltage occurs, the amplifier could be damaged depending on the magnitude of the applied voltage and the magnitude of the fault current. Although not shown here, when the input voltage exceeds either supply by more than 0.6 V, pn-junctions internal to the AD8531/AD8532/AD8534 energize allowing current to flow from the input to the supplies. As illustrated in the simplified equivalent input circuit (Figure 32), the AD8531/ AD8532/AD8534 does not have any internal current limiting resistors, so fault currents can quickly rise to damaging levels. REV. D -9- AD8531/AD8532/AD8534 This input current is not inherently damaging to the device as long as it is limited to 5 mA or less. For the AD8531/AD8532/ AD8534, once the input voltage exceeds the supply by more than 0.6 V the input current quickly exceeds 5 mA. If this condition continues to exist, an external series resistor should be added. The size of the resistor is calculated by dividing the maximum overvoltage by 5 mA. For example, if the input voltage could reach 10 V, the external resistor should be (10 V/ 5 mA) = 2 kW. This resistance should be placed in series with either or both inputs if they are exposed to an overvoltage condition. For more information on general overvoltage characteristics of amplifiers refer to the 1993 Seminar Applications Guide, available from the Analog Devices Literature Center. Output Phase Reversal 5V AD8532 VIN 100mV p-p RS 5 CS 1F CL 47nF VOUT Figure 36. Snubber Network Compensates for Capacitive Loads Some operational amplifiers designed for single-supply operation exhibit an output voltage phase reversal when their inputs are driven beyond their useful common-mode range. The AD8531/AD8532/AD8534 is free from reasonable input voltage range restrictions provided that input voltages no greater than the supply voltage rails are applied. Although the device's output will not change phase, large currents can flow through internal junctions to the supply rails, as was pointed out in the previous section. Without limit, these fault currents can easily destroy the amplifier. The technique recommended in the input overvoltage protection section should therefore be applied in those applications where the possibility of input voltages exceeding the supply voltages exists. Capacitive Load Drive The first step is to determine the value of the resistor, RS. A good starting value is 100 W. This value is reduced until the small-signal transient response is optimized. Next, CS is determined--10 mF is a good starting point. This value is reduced to the smallest value for acceptable performance (typically, 1 mF). For the case of a 47 nF load capacitor on the AD8531/AD8532/ AD8534, the optimal snubber network is a 5 W in series with 1 mF. The benefit is immediately apparent as seen in the scope photo in Figure 37. The top trace was taken with a 47 nF load and the bottom trace with the 5 W--1 mF snubber network in place. The amount of overshoot and ringing is dramatically reduced. Table I below illustrates a few sample snubber networks for large load capacitors: Table I. Snubber Networks for Large Capacitive Loads Load Capacitance (CL) 0.47 nF 4.7 nF 47 nF Snubber Network (RS, CS) 300 W, 0.1 mF 30 W, 1 mF 5 W, 1 mF The AD8531/AD8532/AD8534 exhibits excellent capacitive load driving capabilities. It can drive up to 10 nF directly as shown in Figures 21 through 24. However, even though the device is stable, a capacitive load does not come without a penalty in bandwidth. As shown in Figure 35, the bandwidth is reduced to under 1 MHz for loads greater than 10 nF. A "snubber" network on the output won't increase the bandwidth, but it does significantly reduce the amount of overshoot for a given capacitive load. A snubber consists of a series R-C network (RS, CS), as shown in Figure 36, connected from the output of the device to ground. This network operates in parallel with the load capacitor, CL, to provide phase lag compensation. The actual value of the resistor and capacitor is best determined empirically. 4 VS = 3.5 3 2.5V RL = 1k TA = 25 C 50mV 100 47nF LOAD ONLY 90 SNUBBER IN CIRCUIT 10 0% 50mV 10 s BANDWIDTH - MHz 2.5 2 1.5 1 0.5 0 0.01 Figure 37. Overshoot and Ringing Is Reduced by Adding a Snubber Network in Parallel with the 47 nF Load 0.1 1 CAPACITIVE LOAD - nF 10 100 Figure 35. Unity-Gain Bandwidth vs. Capacitive Load -10- REV. D AD8531/AD8532/AD8534 A High Output Current, Buffered Reference/Regulator Many applications require stable voltage outputs relatively close in potential to an unregulated input source. This "low dropout" type of reference/regulator is readily implemented with a rail-to-rail output op amp, and is particularly useful when using a higher current device such as the AD8531/AD8532/AD8534. A typical example is the 3.3 V or 4.5 V reference voltage developed from a 5 V system source. Generating these voltages requires a three terminal reference, such as the REF196 (3.3 V) or the REF194 (4.5 V), both which feature low power, with sourcing outputs of 30 mA or less. Figure 38 shows how such a reference can be outfitted with an AD8531/AD8532/AD8534 buffer for higher currents and/or voltage levels, plus sink and source load capability. VS 5V C1 0.1 F R2 10k 1% U2 To scale VOUT2 to another (higher) output level, the optional resistor R3 (shown dotted) is added, causing, the new VOUT1 to become: E R2 VOUT 1 =VOUT 2 A1+ E R3 The circuit can either be used as shown, as a 5 V to 3.3 V reference/regulator, or with ON/OFF control. By driving Pin 3 of U1 with a logic control signal as noted, the output is switched ON/OFF. Note that when ON/OFF control is used, resistor R4 must be used with U1 to speed ON-OFF switching. A Single-Supply, Balanced Line Driver AD8531 VOUT1 = 3.3V @ 100mA R1 10k 1% C3 0.1 F VC ON/OFF CONTROL INPUT CMOS HI (OR OPEN) = ON LO = OFF VS COMMON 3 R3 (SeeText) 6 VOUT2 = 3.3V C2 0.1 F C5 100 F/16V TANTALUM R5 0.2 2 U1 REF196 4 C4 1F R4 3.3k The circuit in Figure 39 is a unique line driver circuit topology used in professional audio applications and has been modified for automotive and multimedia audio applications. On a single 5 V supply, the line driver exhibits less than 0.7% distortion into a 600 W load from 20 Hz to 15 kHz (not shown) with an input signal level of 4 V p-p. In fact, the output drive capability of the AD8531/AD8532/AD8534 maintains this level for loads as small as 32 W. For input signals less than 1 V p-p, the THD is less than 0.1%, regardless of load. The design is a transformerless, balanced transmission system where output common-mode rejection of noise is of paramount importance. As with the transformer-based system, either output can be shorted to ground for unbalanced line driver applications without changing the circuit gain of 1. Other circuit gains can be set according to the equation in the diagram. This allows the design to be easily configured for inverting, noninverting or differential operation. R3 10k 2 3 A2 1 R6 10k R5 50 C3 47 F VO1 VOUT COMMON Figure 38. A High Output Current Reference/Regulator The low dropout performance of this circuit is provided by stage U2, an AD8531 connected as a follower/buffer for the basic reference voltage produced by U1. The low voltage saturation characteristic of the AD8531/AD8532/AD8534 allows up to 100 mA of load current in the illustrated use, as a 5 V to 3.3 V converter with good dc accuracy. In fact, the dc output voltage change for a 100 mA load current delta measured less than 1 mV. This corresponds to an equivalent output impedance of < 0.01 W. In this application, the stable 3.3 V from U1 is applied to U2 through a noise filter, R1-C1. U2 replicates the U1 voltage within a few millivolts, but at a higher current output at VOUT1, with the ability to both sink and source output current(s) --unlike most IC references. R2 and C2 in the feedback path of U2 provide additional noise filtering. Transient performance of the reference/regulator for a 100 mA step change in load current is also quite good and is largely determined by the R5-C5 output network. With values as shown, the transient is about 20 mV peak and settles to within 2 mV in less than 10 ms for either polarity. Although room exists for optimizing the transient response, any changes to the R5-C5 network should be verified by experiment to preclude the possibility of excessive ringing with some capacitor types. R2 10k 5V C1 22 F VIN 2 3 A1 1 R7 10k 12V 6 7 A1 5 R9 100k R12 10k 7 R13 10k 5V R8 100k C2 1F RL 600 R1 10k A1, A2 = 1/2 AD8532 GAIN = R3 R2 R10 10k R11 10k 6 5 A2 R14 50 C4 47 F VO2 SET: R7, R10, R11 = R2 SET: R6, R12, R13 = R3 Figure 39. A Single-Supply, Balanced Line Driver for Multimedia and Automotive Applications REV. D -11- AD8531/AD8532/AD8534 A Single-Supply Headphone Amplifier Because of its speed and large output drive, the AD8531/AD8532/ AD8534 makes an excellent headphone driver, as illustrated in Figure 40. Its low supply operation and rail-to-rail inputs and outputs give a maximum signal swing on a single 5 V supply. To ensure maximum signal swing available to drive the headphone, the amplifier inputs are biased to V+/2, which in this case is 2.5 V. The 100 kW resistor to the positive supply is equally split into two 50 kW resistors, with their common point bypassed by 10 mF to prevent power supply noise from contaminating the audio signal. The audio signal is then ac-coupled to each input through a 10 mF capacitor. A large value is needed to ensure that the 20 Hz audio information is not blocked. If the input already has the proper dc bias, the ac coupling and biasing resistors are not required. A 270 mF capacitor is used at the output to couple the amplifier to the headphone. This value is much larger than that used for the input because of the low impedance of the headphones, which can range from 32 W to 600 W. An additional 16 W resistor is used in series with the output capacitor to protect the op amp's output stage by limiting capacitor discharge current. When driving a 48 W load, the circuit exhibits less than 0.3% THD+N at output drive levels of 4 V p-p. V 5V V 5V 50k 1 F/0.1 F In this two-way example, the LO signal is a dc-500 Hz LP woofer output, and the HI signal is the HP (>500 Hz) tweeter output. U1B forms an LP section at 500 Hz, while U1A provides a HP section, covering frequencies 500 Hz. C1 0.01 F R1 31.6k C2 0.01 F 3 VIN RIN 100k CIN 10 F R2 31.6k 2 4 VS U1A 100k 1 R3 49.9 270 F + 500Hz AND UP HI AD8532 R5 31.6k R6 31.6k R7 15.8k C4 0.02 F 6 7 5 U1B C3 0.01 F R4 49.9 270 F + DC - 500Hz LO 100k VS 100k 100k 10 F AD8532 VS 0.1 F TO U1 100 F/25V 5V COM 50k LEFT INPUT 10 F 1/2 AD8532 16 270 F Figure 41. A Single-Supply, Two-Way Active Crossover LEFT HEADPHONE 50k 10 F 100k V 50k The crossover example frequency of 500 Hz can be shifted lower or higher by frequency scaling of either resistors or capacitors. In configuring the circuit for other frequencies, complementary LP/HP action must be maintained between sections, and component values within the sections must be in the same ratio. Table II provides a design aid to adaptation, with suggested standard component values for other frequencies. Table II. RC Component Selection for Various Crossover Frequencies 50k RIGHT INPUT 10 F 1/2 AD8532 16 270 F RIGHT HEADPHONE 50k 10 F Crossover Frequency (Hz) 100 200 319 500 1k 2k 5k 10 k R1/C1 (U1A)1 R5/C3 (U1B)2 160 kW/0.01 mF 80.6 kW/0.01 mF 49.9 kW/0.01 mF 31.6 kW/0.01 mF 16 kW/0.01 mF 8.06 kW/0.01 mF 3.16 kW/0.01 mF 1.6 kW/0.01 mF 100k Figure 40. A Single-Supply, Stereo Headphone Driver A Single-Supply, Two-Way Loudspeaker Crossover Network Active filters are useful in loudspeaker crossover networks for reasons of small size, relative freedom from parasitic effects, the ease of controlling low/high channel drive and the controlled driver damping provided by a dedicated amplifier. Both Sallen-Key (SK) and multiple-feedback (MFB) filter architectures are useful in implementing active crossover networks. The circuit shown in Figure 41 is a single-supply, two-way active crossover which combines the advantages of both filter topologies. This active crossover exhibits less than 0.4% THD+N at output levels of 1.4 V rms using general purpose unity-gain HP/LP stages. NOTES Applicable for filter a = 2. 1 For Sallen-Key stage U1A: R1 = R2, and C1 = C2, etc. 2 For Multiple Feedback stage U1B: R6 = R5, R7 = R5/2, and C4 = 2C3. For additional information on the active filters and active crossover networks, please consult the data sheet for the OP279, a dual rail-to-rail high-output current operational amplifier. -12- REV. D AD8531/AD8532/AD8534 Direct Access Arrangement for Telephone Line Interface Figure 42 illustrates a 5 V only transmit/receive telephone line interface for 600 W transmission systems. It allows full duplex transmission of signals on a transformer coupled 600 W line in a differential manner. Amplifier A1 provides gain that can be adjusted to meet the modem output drive requirements. Both A1 and A2 are configured to apply the largest possible signal on a single supply to the transformer. Because of the high output current drive and low dropout voltage of the AD8531/AD8532/ AD8534s, the largest signal available on a single 5 V supply is approximately 4.5 V p-p into a 600 W transmission system. Amplifier A3 is configured as a difference amplifier for two reasons: (1) It prevents the transmit signal from interfering with the receive signal and (2) it extracts the receive signal from the transmission line for amplification by A4. A4's gain can be adjusted in the same manner as A1's to meet the modem's input signal requirements. Standard resistor values permit the use of SIP (Single In-line Package) format resistor arrays. P1 Tx GAIN ADJUST TO TELEPHONE LINE 1:1 ZO 600 T1 MIDCOM 671-8005 6.2V 6.2V R2 9.09k 2 A1 3 R1 10k R3 360 R5 10k 2k 1 C1 0.1 F TRANSMIT TxA 5V DC R6 10k 6 7 A2 5 10 F R9 10k 2 3 A3 1 R10 10k R13 10k R14 14.3k 6 5 A4 R7 10k R8 10k P2 Rx GAIN ADJUST R11 10k R12 10k RECEIVE RxA 2k 7 C2 0.1 F A1, A2 = 1/2 AD8532 A3, A4 = 1/2 AD8532 Figure 42. A Single-Supply Direct Access Arrangement for Modems REV. D -13- AD8531/AD8532/AD8534 * AD8531/AD8532/AD8534 SPICE Macro-model 3/96, REV. D * 5-Volt Version ARG / ADSC * * Copyright 1996 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance of the terms and provisions in the License * Statement. * * Node assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD8531/AD8532/AD8534_5 1 2 99 50 40 * * INPUT STAGE * M1 3 2 6 50 NIX L=6U W=25U M2 4 7 6 50 NIX L=6U W=25U M3 8 2 5 5 PIX L=6U W=25U M4 9 7 5 5 PIX L=6U W=25U EOS 7 1 POLY(1) 25 98 5E-3 0.451 IIN1 1 98 5P IIN2 2 98 5P IOS 2 1 0.5P I1 99 5 50U I2 6 50 50U R1 99 3 4.833K R2 99 4 4.833K R3 8 50 4.833K R4 9 50 4.833K D3 5 99 DX D4 50 6 DX * * GAIN STAGE * EREF 98 0 POLY(2) 99 0 50 0 0 0.5 +0.5 G1 98 21 POLY(2) 4 3 9 8 0 +145U +145U RG 21 98 18.078E6 CC 21 40 14P D1 21 22 DX D2 23 21 DX V1 99 22 1.37 V2 23 50 1.37 * * COMMON MODE GAIN STAGE * ECM 24 98 POLY(2) 1 98 2 98 0 0.5 +0.5 R5 24 25 1E6 R6 25 98 10K C1 24 25 0.75P * * OUTPUT STAGE * ISY 99 50 450.4U GSY 99 50 POLY(1) 99 50 -3.334E-4 6.667E-5 EP 99 39 POLY(1) 98 21 0.78925 1 EN 38 50 POLY(1) 21 98 0.78925 1 M15 40 39 99 99 POX L=1.5U W=1500U M16 40 38 50 50 NOX L=1.5U W=1500U C15 40 39 50P C16 40 38 50P .MODEL DX D(RS=1 CJO=0.1P) .MODEL NIX NMOS(VTO=0.75 KP=205.5U RD=1 RS=1 RG=1 RB=1 +CGSO=4E-9 +CGDO=4E-9 CGBO=16.667E-9 CBS=2.34E-13 CBD=2.34E-13) .MODEL NOX NMOS(VTO=0.75 KP=195U RD=.5 RS=.5 RG=1 RB=1 +CGSO=66.667E-12 +CGDO=66.667E-12 CGBO=125E-9 CBS=2.34E-13 CBD=2.34E-13) .MODEL PIX PMOS(VTO=-0.75 KP=205.5U RD=1 RS=1 RG=1 RB=1 +CGSO=4E-9 +CGDO=4E-9 CBDO=16.667E-9 CBS=2.34E-13 CBD=2.34E-13) .MODEL POX PMOS(VTO=-0.75 KP=195U RD=.5 RS=.5 RG=1 RB=1 +CGSO=66.667E-12 +CGDO=66.667E-12 CGBO=125E-9 CBS=2.34E-13 CBD=2.34E-13) .ENDS -14- REV. D AD8531/AD8532/AD8534 OUTLINE DIMENSIONS 8-Lead Thin Shrink Small Outline Package [TSSOP] (RU-8) Dimensions shown in millimeters 3.10 3.00 2.90 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters 5.10 5.00 4.90 8 5 14 8 4.50 4.40 6.40 BSC 4.30 1 4 4.50 4.40 4.30 1 7 6.40 BSC PIN 1 0.15 0.05 0.65 BSC 1.20 MAX SEATING 0.20 PLANE 0.09 8 0 PIN 1 1.05 1.00 0.80 0.75 0.60 0.45 0.65 BSC 1.20 MAX 0.15 0.05 0.30 0.19 0.20 0.09 8 0 0.30 COPLANARITY 0.19 0.10 SEATING COPLANARITY PLANE 0.10 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153AA COMPLIANT TO JEDEC STANDARDS MO-153AB-1 5-Lead Plastic Surface Mount Package [SC70] (KS-5) Dimensions shown in millimeters 2.00 BSC 5-Lead Plastic Surface-Mount Package [SOT-23] (RT-5) Dimensions shown in millimeters 2.90 BSC 5 4 5 4 1.25 BSC 1 2 3 2.10 BSC 1.60 BSC 1 2 3 2.80 BSC PIN 1 1.00 0.90 0.70 0.10 0.00 0.30 0.15 0.65 BSC 1.10 MAX 0.22 0.08 SEATING PLANE 0.46 0.36 0.26 1.30 1.15 0.90 PIN 1 0.95 BSC 1.90 BSC 1.45 MAX 10 0 COMPLIANT TO JEDEC STANDARDS MO-203AA 0.15 MAX 0.50 0.30 SEATING PLANE 0.22 0.08 0.60 0.45 0.30 COMPLIANT TO JEDEC STANDARDS MO-178AA 8-Lead MSOP Package [MSOP] (RM-8) Dimensions shown in millimeters 3.00 BSC 8-Lead Standard Small Outline Package [SOIC] Narrow Body (RN-8) Dimensions shown in millimeters and (inches) 5.00 (0.1968) 4.80 (0.1890) 8 5 3.00 BSC 1 4 4.90 BSC 8 5 4 4.00 (0.1574) 3.80 (0.1497) 1 6.20 (0.2440) 5.80 (0.2284) PIN 1 0.65 BSC 0.15 0.00 0.38 0.22 COPLANARITY 0.10 1.10 MAX 8 0 0.80 0.40 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY SEATING 0.10 PLANE 1.75 (0.0688) 1.35 (0.0532) 8 0.25 (0.0098) 0 0.19 (0.0075) 0.50 (0.0196) 0.25 (0.0099) 45 0.23 0.08 SEATING PLANE 0.51 (0.0201) 0.33 (0.0130) 1.27 (0.0500) 0.41 (0.0160) COMPLIANT TO JEDEC STANDARDS MO-187AA COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN REV. D -15- AD8531/AD8532/AD8534 OUTLINE DIMENSIONS 14-Lead Standard Small Outline Package [SOIC] Narrow Body (RN-14) Dimensions shown in millimeters and (inches) 8.75 (0.3445) 8.55 (0.3366) 4.00 (0.1575) 3.80 (0.1496) 14 1 8 7 6.20 (0.2441) 5.80 (0.2283) 0.25 (0.0098) 0.10 (0.0039) COPLANARITY 0.10 1.27 (0.0500) BSC 1.75 (0.0689) 1.35 (0.0531) 0.50 (0.0197) 0.25 (0.0098) 45 0.51 (0.0201) 0.33 (0.0130) SEATING PLANE 8 0.25 (0.0098) 0 1.27 (0.0500) 0.40 (0.0157) 0.19 (0.0075) CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Revision History Location 10/02--Data Sheet changed from REV. C to REV. D. Page Deleted 8-Lead PDIP (N-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Deleted 14-Lead PDIP (N-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Edits to Figure 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 -16- REV. D PRINTED IN U.S.A. C01099-0-10/02(D) |
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